1. Field of the Invention
The present invention relates to methods of fabricating a dielectric layer used in a semiconductor device and, more particularly, to methods of fabricating a high-k dielectric layer having reduced impurities.
2. Description of the Related Art
In a semiconductor device, a dielectric layer has a variety of uses. Typically, the dielectric layer is used as a gate dielectric layer of a MOS field effect transistor. To normally operate the semiconductor device, the gate dielectric layer should be able to maintain the capacitance (C) of the device at a suitable level. The capacitance of the dielectric layer is defined as follows: C=ε·A/d (where C is capacitance, ε is a dielectric constant, A is a surface area of the dielectric layer, and d is the thickness of the dielectric layer). That is, the capacitance of the dielectric layer is directly proportional to the dielectric constant and the surface area of the dielectric layer and is inversely proportional to the thickness of the dielectric layer. As semiconductor devices have become more highly integrated, the area of a unit cell of the semiconductor device has been reduced and therefore the surface area of the gate dielectric layer has also been reduced. Hence, there is a need to compensate for the associated reduction of the capacitance of the dielectric layer due to the reduced surface area of the gate dielectric layer. The reduced capacitance of the dielectric layer may be compensated for by decreasing the thickness (d) of the dielectric layer and/or by using a higher-k dielectric material. In cases where the thickness of the dielectric layer is reduced, however, there often occurs a problem in that leakage current is increased due to the reduced thickness of the dielectric layer. Accordingly, in order to maintain the proper capacitance of the dielectric layer without increasing the leakage current, a dielectric material having a higher-k dielectric constant is required.
High-k dielectric materials applicable to the gate dielectric layer of a semiconductor device conventionally include an aluminum oxide (Al2O3) layer, a hafnium oxide (HfO2) layer, a zirconium oxide (ZrO2) layer, a tantalum oxide (Ta2O5) layer, a titanium oxide (TiO2) layer, etc. Further, dielectric materials having an ultra-high k dielectric constant are known including a barium strontium titanate (BST) layer, a lead zirconate titanate (PZT) layer, etc. However, the application of a new dielectric material should be determined in conjunction with the related considerations of compatibility, reliability, productivity, etc. with a fabricating process of the conventional semiconductor device as well as a high-k dielectric constant.
From this point of view, when one of the foregoing high-k dielectric materials is used as the gate dielectric layer, one or more of the following problems may occur. In the case of the BST layer, the titanium oxide layer, the tantalum oxide layer, etc., reactivity with a silicon substrate is relatively high; and, thus, the interfacial properties between the gate dielectric layer and the silicon substrate become poor, thereby increasing the leakage current or deteriorating carrier mobility. In the case of the aluminum oxide layer, thermal stability is relatively high but the dielectric constant is relatively low, so that the resulting improvement in capacitance is limited. Further, the aluminum oxide layer has a negative fixed charge, so that it is difficult to control a threshold voltage. In the case of the hafnium oxide layer, the zirconium oxide layer, etc., these dielectric layers are known to become partially crystallized by the heat (annealing) treatment step that typically follows formation of the dielectric layer, thereby increasing the leakage current.
In the meanwhile, a hafnium silicate (HfSiO2) layer has been developed as a promising material for the gate dielectric layer. The hafnium silicate layer has good properties as the gate dielectric layer. For example, the NMOS threshold voltage and the current performance of hafnium silicate layers are equivalent to those of a silicon oxynitride (SiON) layer. The hafnium silicate layer may be formed by a metal-organo chemical vapor deposition (MOCVD) method or an atomic layer deposition (ALD) method. In the case of the MOCVD method, it is difficult to control the thickness and the composition of the hafnium silicate layer. On the other hand, in the case of the ALD method, the hafnium silicate layer is formed as a sequence of atomic layers, so that it is possible to precisely control the thickness of the completed hafnium silicate layer. The ALD method is typically performed at a relatively low temperature. For reference, there has also been disclosed a method of forming the hafnium silicate layer by forming a nano-laminated structure on which a hafnium oxide layer and a silicon oxide layer are alternately stacked using the ALD method, in U.S. Pat. No. 6,627,503, entitled “Multilayer dielectric stack,” which patent is incorporated herein by reference.
However, because the ALD method is performed at a relatively low temperature, impurities such as carbon (C), chlorine (Cl), etc. injected from source gas(es) may remain in the hafnium silicate layer after formation, thereby contaminating the hafnium silicate layer and impairing the performance of the resulting semiconductor device. Accordingly, there is a need for an alternative technique for preparing a high-quality, high-k dielectric layer of controlled thickness while substantially eliminating contamination by impurities.